1. Field of the Invention
The present invention relates to semiconductor storage device and, more particularly, to the formation of a floating gate of a flash memory.
2. Description of Related Art
A flash memory is a nonvolatile memory capable of retaining stored data even after its power is turned OFF. The cell structure of the flash memory widely varies, but basically includes a MOS transistor having a double gate structure in which a floating gate is provided between a control gate and a silicon substrate.
The storing mechanism is such that the voltage of the control gate at which current starts to flow into a memory cell differs depending on whether electrons are present or absent in the floating gate. The different voltages allow 1 and 0 of logic data to be stored. The floating gate is in a floating state, being fully surrounded by an insulating film; therefore, when the power is turned OFF after electrons are electrically charged into or discharged from the floating gate, the electrons in the floating gate do not leak out or no additional electrons enter the floating gate. This is the mechanism of a nonvolatile memory.
One of the wide variety of cell structures is shown in FIG. 6. In the cell structure, a source line diffusion layer 57 and a drain line diffusion layer 77 are formed on a silicon substrate, and a floating gate 65 and a word line 70 providing a control gate are formed through the intermediary of a gate oxide film 51. The word line 70 is isolated from the floating gate 65 through the intermediary of a tunnel oxide film 69 and a thermally-oxidized film 54. A source line 68 is formed on the source line diffusion layer 57. The portion of the floating gate 65 that opposes the word line 70 has a pointed distal end. Hereinafter, the pointed end portion of the floating gate 65 will be referred to simply as a pointed portion 60.
In the flash memory of this type having the structure described above, in a writing mode, the source is set to 0 volt, while the drain and the word line are set at a high voltage. This causes electrons to flow from the source to the drain at a high electric field, generating hot electrons capable of crossing over the energy barrier from a silicon surface to an oxide film in the vicinity of the drain. The hot electrons are drawn by the high voltage of the word line into the floating gate. In an erasing mode, a voltage is applied to the word line shown in FIG. 6 to concentrate electric charges at the pointed portions of the floating gate to draw out electrons from the floating gate.
Hence, in the flash memory having such a structure, it is important to form the pointed portion of the floating gate with high accuracy and stability. The pointed portion considered to be most preferable has an angle of about 45 degrees and a height of about 20 nm to 30 nm.
FIG. 7 illustrates a conventional process for forming the pointed portion. An 8 nm-thick gate oxide film 51, an 80 nm-thick poly-silicon film 52, and a 300 nm-thick silicon nitride film 53 are formed in this sequence on a silicon substrate 50. Using a photoresist, a floating gate and the region planned for a source are formed on the silicon nitride film 53 by patterning. This is used as the mask to dry-etch the silicon nitride film 53 by a dry-etching apparatus, and the resist is ashed by an ashing apparatus, as shown in FIG. 7A.
Then, by using the etched silicon nitride film 53 as a mask, the poly-silicon film 52 is etched to a depth of about 30 nm at a tapering angle of 45 degrees by, for example, a downflow, microwave type etching apparatus under a condition of a 0.5-Torr pressure, an etching gas CF4/O2=100/30 sccm, an 800-W microwave power, a 60xc2x0 C. lower electrode, and a 15-second etching time (refer to FIG. 7B).
Subsequently, a thermally-oxidized film 54 of about 6 nm is deposited at 850xc2x0 C. on the front surface of the poly-silicon film 52, as shown in FIG. 7C. Then, a TEOS (tetraethoxysilane)-NSG (non-doped silicate glass) film of about 180 nm is deposited on the entire surface by the LPCVD method, and an NSG spacer 55 is formed by a dry etching apparatus, as shown in FIG. 8A. Furthermore, the poly-silicon film 52 is etched by a dry etching apparatus by using the silicon nitride film 53 and the NSG spacer 55 as the masks, as shown in FIG. 8B.
Thereafter, the TEOS-NSG film is formed to a thickness of about 60 nm on the entire surface by the LPCVD process, and an NSG spacer 56 is formed by a dry etching apparatus. The gate oxide film 51 is etched, then a source diffusion region 57 is formed by ion implantation, as shown in FIG. 8C. Next, a poly-silicon film is deposited on the entire surface, and etched back by a dry etching apparatus to form a poly-silicon plug 58. Thereafter, a thermally-oxidized film 59 having a thickness of about 10 nm is deposited on the front surface of the poly-silicon plug 58 at 850xc2x0 C., as shown in FIG. 8D. Next, the oxide film is removed from the front surface of the silicon nitride film 53 with, for example, a 5% hydrofluoric acid solution, for 45 seconds, then the silicon nitride film 53 is removed by applying, for example, hot phosphoric acid (H3PO4) of 150xc2x0 C. for about 4000 seconds (30% over-etching), as shown in FIG. 9A.
In the following step, by using the NSG spacer 56 and the thermally-oxidized film 59 as the masks, the poly-silicon film 52 is dry-etched to form the pointed portion 60 (FIG. 9B) by, for example, an ICP type (inductively-coupled plasma type) dry-etching apparatus in three steps, namely, a 1st step (a 5-mTorr pressure, an etching gas Cl2=50 sccm, a 250W source power, a 150W bottom power, a 75xc2x0 C. lower electrode temperature, a 5-second etching time), a 2nd step (a 5-mTorr pressure, an etching gas HBr/O2=100/1 sccm, a 200W source power, a 50W bottom power, a 75xc2x0 C. lower electrode temperature, EPD), and a 3rd step (a 60-mTorr pressure, an etching gas HBr/O2/He=100/1/100 sccm, a 250W source power, a 70W bottom power, a 75xc2x0 C. lower electrode temperature, 15-second etching time).
According to the method described above, however, the NSG spacer 56 is retreated sideways by the over-etching when the silicon nitride film 53 is removed by the hot phosphoric acid. During the following process in which the poly-silicon film 52 is dry-etched, the pointed portion 60 is exposed without being covered by the NSG spacer 56. This has been posing a problem in that the pointed portion 60 is undesirably etched, resulting in a defective shape or an insufficient height of the pointed portion 60.
To prevent the NSG spacer 56 from being retreated, there is a method in which the NSG spacer 56 is annealed to make it denser so as to lower the etching rate. However, the temperature increases toward the front surface of the NSG spacer, so that the film quality inevitably differs between the inside and the front surface of the spacer, presenting a problem in that the NSG spacer is defectively shaped due to the over-etching for the removal by hot phosphoric acid, as shown in FIG. 10.
The present invention has been made with a view toward solving the problems with the conventional manufacturing method for a semiconductor storage device, and it is an object of the present invention to provide a novel, improved manufacturing method for a semiconductor storage device that allows a pointed portion to be stably formed as it is originally designed without the danger of being deformed due to accidental etching of the pointed portion or being formed with an insufficient height when forming a floating gate of a flash memory.
To this end, according to a first aspect of the present invention, there is provided a manufacturing method for a semiconductor storage device with a floating gate, including: a first step for etching a poly-silicon film by using a silicon nitride film having an opening as a mask thereby to form a tapered portion that provides a pointed portion of the floating gate later; a second step for depositing a first thermally-oxidized film on the poly-silicon film of the opening of the silicon nitride film; a third step for forming a first NSG film spacer covering the tapered portion of the poly-silicon film on side walls of the opening of the silicon nitride film; a fourth step for adding heat treatment (annealing) to the first NSG film spacer to turn it into a denser film; a fifth step for forming a second NSG film spacer on the inner side of the first NSG film spacer; a sixth step for forming a poly-silicon plug to fill the opening of the silicon nitride film, then depositing a second thermally-oxidized film on the poly-silicon plug; a seventh step for removing only the silicon nitride film; an eighth step for etching the poly-silicon film by using the first NSG film spacer, the second NSG film spacer, and the second thermally-oxidized film as the masks thereby to form a pointed portion of the floating gate; and a ninth step for removing the first NSG film spacer covering the pointed portion.
With this arrangement, the additional NSG spacer for covering the pointed portion is formed on the outer side of the conventional NSG spacer and is annealed, so that the selection ratio of silicon nitride to NSG for hot phosphoric acid etching in the process of removing the silicon nitride film is improved. Moreover, the problem in that the NSG spacer is retreated sideways can be solved; hence, the pointed portion is securely covered in the subsequent step for etching the poly-silicon film to form the pointed portion, thus permitting the pointed portion to be stably formed without being etched.
According to a second aspect of the present invention, there is provided a manufacturing method for a semiconductor storage device with a floating gate, including: a first step for etching a poly-silicon film by using a silicon nitride film having an opening as a mask thereby to form a tapered portion that provides the pointed portion of a floating gate later; a second step for depositing a first thermally-oxidized film on the poly-silicon film of the opening of the silicon nitride film; a third step for forming NSG film spacers on side walls of the opening of the silicon nitride film, then forming a poly-silicon plug to fill the opening of the silicon nitride film, and depositing a second thermally-oxidized film on the poly-silicon plug; a fourth step for removing the silicon nitride film, then depositing an insulating film on the entire surface thereof; a fifth step for forming a spacer of the insulating film that covers the tapered portion of the poly-silicon film on an outer side wall of the NSG film spacer; a sixth step for etching the poly-silicon film by using the insulating film spacer, the NSG film spacer, and the second thermally-oxidized film as the masks thereby to form a pointed portion of the floating gate; and a seventh step for removing the insulating film spacer.
Preferably, the insulating film is a silicon nitride film or an NSG film.
Thus, after the silicon nitride film removing step wherein the NSG spacer is retreated sideways, causing the pointed portion to be exposed, the insulating film spacer that covers the pointed portion is formed on the outer side wall of the NSG spacer. This makes it possible to stably form the pointed portion, preventing the pointed portion from being etched during the poly-silicon etching process.
Moreover, for the NSG spacer for the silicon nitride film or the NSG film used as the insulating film, the selection ratio of poly-silicon to NSG is higher than the selection ratio of poly-silicon to silicon nitride film. This arrangement allows the NSG spacer serving as a mask to have a further stable shape and hence to obtain a good pointed shape when the pointed portion is formed by poly-silicon etching.
According to a third aspect of the present invention, there is provided a manufacturing method for a semiconductor storage device with a floating gate, including: a first step for etching a poly-silicon film under a silicon nitride film by using the silicon nitride film having an opening as a mask thereby to form a tapered portion that provides the floating gate later; a second step for depositing a first thermally-oxidized film on the poly-silicon film of the opening of the silicon nitride film; a third step for forming an NSG film that covers the tapered portion of the poly-silicon film and that has been processed into a dense film by heat treatment on a side wall of the opening of the silicon nitride film; a fourth step for etching an altered layer of the surfaces of the NSG film spacer and the silicon nitride film; a fifth step for forming a poly-silicon plug to fill the opening of the silicon nitride film, then depositing a second thermally-oxidized film on the poly-silicon plug; a sixth step for removing the silicon nitride film; and a seventh step for etching the poly-silicon film by using the NSG film spacer and the second thermally-oxidized film as the masks thereby to form the pointed portion of the floating gate.
Thus, the portions of the surface layers of the NSG spacer and the silicon nitride film at which the rate of etching with hot phosphoric acid is lower because of heat treatment, are removed. This obviates the need for over-etching in the hot phosphoric acid etching process, thus eliminating the cause for forming an NSG spacer with a defective shape. Therefore, a stable pointed shape can be achieved in the subsequent etching process of the poly-silicon film that provides the pointed portion.
Preferably, when the portion of the surface layer of the NSG spacer at which the etching rate is lower, as described above, is removed, the emission intensity of the emission wavelength of CO, which is a main reaction byproduct of the NSG, is monitored to determine the completion of the altered layer produced by carrying out heat treatment of the NSG film side wall spacer. This makes it possible to accommodate variations in film quality and fluctuation in etching rate, permitting further stable shaping of the NSG spacers and a better shape of the pointed portion to be accomplished.